//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2008-2012 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
// Version and Release Control Information:
//
// File Revision       : 127275
// File Date           :  2012-03-19 15:37:15 +0000 (Mon, 19 Mar 2012)
// Release Information : PL401-r0p1-00eac0
//------------------------------------------------------------------------------
// Purpose : This is a mux tree
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//
//        *** AUTOMATICALLY GENERATED, ONLY MODIFY MARKED SECTIONS ***
//
//  Config :
//           o  FIFO Depth  = 2
//
//
//------------------------------------------------------------------------------



module nic400_ib_chiplink_slv_axi4_tpv_ib_ar_fifo_wr_mux_ysyx_rv32
(
  // Inputs
  in_0,
  in_1,

  sel,

  // Outputs
  d_out
);

//-----------------------------------------------------------------------------
// Port Declarations
//-----------------------------------------------------------------------------
  input  [60:0]   in_0;
  input  [60:0]   in_1;

  input           sel;

  output [60:0]   d_out;

//-----------------------------------------------------------------------------
// Wire Declarations
//-----------------------------------------------------------------------------
      

//-----------------------------------------------------------------------------
// Main Code
//-----------------------------------------------------------------------------
      nic400_ib_chiplink_slv_axi4_tpv_ib_ar_fifo_wr_mux2_ysyx_rv32 u_mux2_0_0
  (
    .din_0 (in_0),
    .din_1 (in_1),
    .sel   (sel),
    .dout  (d_out)
  );


endmodule

// --================================= End ===================================--
